The proposed model of fault current limiter including control circuit to improve power system transient stability

In this paper, the operation of proposed configuration of fault current limiter to improve power system transient stability connected to a single machine infinite bus will be studied. The method employed to calculate the optimum resistance value to reach the maximum transient stability will be presented. To demonstrate the operation of proposed structure and its effectiveness on power system transient stability, the simulation result will be carried out in PSCAD/EMTDC software. The results show the improvement of power system transient stability when the optimum resistance utilised. In fact, the proposed fault current limiter not only enhance the transient stability after fault removal, but also keep the system stable if it is subjected to an unusual permanent fault.