Design Decisions in the PCM-1

The PCM-1 processor has an innovative computer architecture for the fast execution of functional programming languages by graph reduction. Expected performance is about 50 Mips (internally) realizing 0.5 million reductions/s. RISC principles have influenced the processor design. This paper analyses significant architectural decisions made in the PCM-1 and show how is RISC-like design achieves high performance. The application of RISC principles to a machine not designed for procedural programming are discussed, including the instruction sequencing, accommodation of slow operations such as addition, the substitution of software analysis for hardware, a cache on the chip, and matching of the register file and control store cycles.