University Of Tasmania
Validation_and_Verification_of_Software_Design_Using_FSP.pdf (522.99 kB)

Validation and Verification of Software Design using Finite State Process

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posted on 2023-05-26, 07:47 authored by Stanton, SC
This thesis aims to evaluate the effectiveness of a formal language (Finite State Process) automated verification tool (Labelled Transition System Analyser) at finding and resolving errors in design models of software. FSP is used to model the Lift Problem from a specification refined by validation. The specification is mapped to a finite state domain and tested for errors - in the mapping, in the understanding of the initial requirements, in the accuracy of the initial requirements, and in the concurrency properties of the identified co-operating entities. Exposition of errors refines (validates) the initial description, and drives their resolution giving rise to an evolutionary corrected model; upon exit of iterative analysis this is mapped to UML behavioural diagrams forming Implementation Specifications.


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