A Fast VLSI Implementation of a FIFO Queue

The paper describes a hardware implementation in nMOS of a first-in, first-out (FIFO) queue. The implementation has independently operating insertion and extraction logic which is capable of achieving high speeds of less than 20Ons per operation, and may be entirely contained on a single chip. A regular cellular structure is described which is capable of extension both in the direction of wider queued items and in the direction of maximum queue size. The implementation was carried out at the University of Tasmania by the first five authors under the supervision of the last-named author.